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IT8875F pci parallel port preliminary specification v0.1
copyright ? 200 1 ite, inc. this is preliminary document release. all specifications are subject to change without notice. the material contained in this document supersedes all previous documentation issued for the related products included herein. please contact ite, inc. for the latest document(s). all sales are subject to ite ? s standard terms and conditions, a copy of which is included in the back of this document. ite, IT8875F is a trademark of ite, inc. all other trademarks are claimed by their respective owners. all specifications are subject to change without notice. additional copies of this manual or other ite literature may be obtained from: ite, inc. phone: (02) 2657-98 96 marketing department fax: (02) 2657-8561, 2657-8576 7f, no. 435, nei hu district, jui kuang rd., taipei 114, taiwan, r.o.c. ite (usa) inc. phone: (408) 530-8860 marketing department fax: (408) 530-8861 1235 midas way sunnyvale, ca 94086 u.s.a. ite (usa) inc. phone: (512) 388-7880 eastern u.s.a. sales office fax: (512) 388-3108 896 summit st., #105 round rock, tx 78664 u.s.a. if you have any marketing or sales questions, please contact: lawrence liu, at ite taiwan: e-mail: lawrence.liu@ite.com.tw , tel: 886-2-26579896 x6071, fax: 886-2-26578561 david lin , at ite u.s.a: e-mail: david.lin@iteusa.com , tel: (408) 530-8860 x238, fax: (408) 530-8861 don gardenhire , at ite eastern usa office: e-mail: don.gardenhire@iteusa.com , tel: (512) 388-7880, fax: (512) 388-3108 to find out more about ite, visit our world wide web at: http://www.ite.com.tw http://www.iteusa.com or e-mail itesupport@ite.com.tw for more product information/services.
www.ite.com.tw IT8875F v0.1 www.iteusa.com i contents contents 1. features ................................ ................................ ................................ ................................ ................... 1 2. general description ................................ ................................ ................................ ................................ .. 3 3. block diagram ................................ ................................ ................................ ................................ .......... 5 4. pin configuration ................................ ................................ ................................ ................................ ...... 7 5. IT8875F pin descriptions ................................ ................................ ................................ .......................... 9 6. power on strapping option s ................................ ................................ ................................ .................. 15 7. system configuration ................................ ................................ ................................ ............................. 17 7.1 overview ................................ ................................ ................................ ................................ ........ 17 7.2 features ................................ ................................ ................................ ................................ ........ 17 8. functional description ................................ ................................ ................................ ............................ 19 8.1 pci slave interface ................................ ................................ ................................ ........................ 19 8.2 pci parity ................................ ................................ ................................ ................................ ..... 19 8.3 positively decode spaces ................................ ................................ ................................ ............. 19 8.4 smb boot rom configuration ................................ ................................ ................................ ....... 19 8.5 4 chip selects ................................ ................................ ................................ ............................... 21 8.6 parallel port ................................ ................................ ................................ ................................ .. 21 9. register descriptions ................................ ................................ ................................ .............................. 23 9.1 configuration register map ................................ ................................ ................................ .......... 23 9.2 access configuration registers ................................ ................................ ................................ ..... 24 9.3 configuration register descriptions ................................ ................................ ............................... 26 9.3.1 device/vendor id register (idr) ? offset 00h ................................ ................................ ... 26 9.3.2 status / command register (scr) ? offset 04h ................................ ............................... 26 9.3.3 class code/ revision id register (ccridr) ? offset 08h ................................ ................ 27 9.3.4 header type/ mlt/ cache line size register (hmcr) ? offset 0ch ................................ 27 9.3.5 pci space_0 base address register (ps0bar) ? offset 10h ................................ .......... 28 9.3.6 pci space_1 base address register (ps1bar) ? offset 14h ................................ .......... 28 9.3.7 pci space_2 base address register (ps2bar) ? offset 18h ................................ .......... 29 9.3.8 pci space_3 base addre ss register (ps3bar) ? offset 1ch ................................ .......... 29 9.3.9 pci space_4 base address register (ps4bar) ? offset 20h ................................ .......... 30 9.3.10 pci space_5 base address register (ps5bar) ? offset 24h ................................ .......... 30 9.3.11 sub-system device id / sub-system vendor id ? offset 2ch ................................ ........... 31 9.3.12 interrupt pin/line register (intr) ? offset 3ch ................................ ................................ 31 9.3.13 global control_1 register (gc1r) ? offset 40h ................................ ............................... 32 9.3.14 global control_2 register (gc2r) ? offset 44h ................................ ............................... 33 9.3.15 pci space_1/0 remap register (rmp10r) ? offset 50h ................................ ................. 34 9.3.16 pci space_3/2 remap register (rmp32r) ? offset 54h ................................ ................. 35 9.3.17 pci space_5/4 remap register (rmp54r) ? offset 58h ................................ ................. 36 9.3.18 positively decoded i/o_space_0 register (posio0r) ? offset 60h ................................ . 37 9.3.19 positively decoded i/o_spa ce_1 register (posio1r) ? offset 64h ................................ . 37 9.3.20 positively decoded i/o_space_2 register (posio2r) ? offset 68h ................................ . 38 9.3.21 positively decoded i/o_space_3 register (posio3r) ? offset 6ch ................................ 38 9.3.22 positively decoded i/o_space_4 register (posio4r) ? offset 70h ................................ . 39 9.3.23 intc base address register (intcbar) ? offset 78h ................................ ..................... 40 9.3.24 internal parallel port base address register (ippbar) ? offset 80h ................................ 40 9.3.25 external devices base address register 1 (xdba1r) ? offset 88h ................................ .. 40 9.3.26 miscellaneous control register (miscr) ? offset 9ch ................................ ..................... 41 9.3.27 undefined register ................................ ................................ ................................ .......... 41
www.ite.com.tw IT8875F v0.1 www.iteusa.com ii it8 875f 10. interrupt controller (intc) ................................ ................................ ................................ ...................... 43 10.1 features ................................ ................................ ................................ ................................ ....... 43 10.2 block diagram ................................ ................................ ................................ .............................. 43 10.3 register descriptions ................................ ................................ ................................ ................... 44 10.3.1 interrupt request register 1 (irr1r) ? offset intc_base + 0h ................................ ....... 44 10.3.2 interrupt request register 2 (irr2r) ? offset intc_base + 1h ................................ ....... 44 10.3.3 interrupt request register 3 (irr3r) ? offset intc_base + 2h ................................ ....... 44 10.3.4 interrupt mask register 1 (imr1r) ? offset intc_base + 4h ................................ ........... 44 10.3.5 interrupt mask register 2 (imr2r) ? offset intc_base + 5h ................................ ........... 44 10.3.6 interrupt mask register 3 (imr3r) ? offset intc_base + 6h ................................ ........... 45 10.3.7 interrupt edge/level trigger mode register 1 (ier1r) ? offset intc_base + 8h ............. 45 10.3.8 interrupt edge/level trigger mode register 2 (ier2r) ? offset intc_base + 9h ............. 45 10.3.9 interrupt edge/level trigger mode register 3 (ier3r) ? offset intc_base + ah ............. 45 10.3.10 s/w interrupt generate register 1 (sigr1r) ? offset intc_base + ch ....................... 45 10.3.11 s/w interrupt generate register 2 (sigr2r) ? offset intc_base + dh ....................... 45 10.3.12 s/w interrupt generate register 3 (sigr3r) ? offset intc_base + eh ....................... 46 11. parallel port ................................ ................................ ................................ ................................ ............ 47 11.1 overview ................................ ................................ ................................ ................................ ...... 47 11.2 spp and epp modes ................................ ................................ ................................ ................... 47 11.3 epp mode operation ................................ ................................ ................................ .................. 49 11.4 ecp mode operation ................................ ................................ ................................ .................. 50 12. dc characteristics ................................ ................................ ................................ ................................ .. 57 13. package information ................................ ................................ ................................ ............................... 59 14. ordering information ................................ ................................ ................................ ............................... 61 figures figure 9 -1. pci configuration register structure ................................ ................................ .......................... 24 figure 9 -2. pci configuration access mechanism #1 ................................ ................................ ................... 25 figure 10 -1. block diagram of the interrupt controller ................................ ................................ .................. 43 tables table 4 -1. pins listed in numeric order ................................ ................................ ................................ ......... 8 table 5 -1. pin descriptions of supplies signals ................................ ................................ .............................. 9 table 5 -2. pin descriptions of pci bus interface signals ................................ ................................ ................ 9 table 5 -3. pin descriptions of partial isa bus signals ................................ ................................ .................. 11 table 5 -4. pin descriptions of parallel port signals ................................ ................................ ...................... 12 table 5 -5. pin descriptions of miscellaneous signals ................................ ................................ ................... 13 table 9 -1. IT8875F configuration register map ................................ ................................ ........................... 23 table 10 -1. list of intc registers ................................ ................................ ................................ ............... 44 table 11 -1. parallel port connector in different modes ................................ ................................ ................ 47 table 11 -2. address map and bit map for spp and epp modes ................................ ................................ .. 47 table 11 -3. bit map of the ecp registers ................................ ................................ ................................ .... 50 table 11 -4. ecp register definitions ................................ ................................ ................................ ........... 50
www.ite.com.tw IT8875F v0.1 www.iteusa.com iii contents table 11 -5. ecp mode descriptions ................................ ................................ ................................ ............. 51 table 11 -6. ecp pin descriptions ................................ ................................ ................................ ................ 51 table 11 -7. extended control register (ecr) mode and description ................................ ........................... 53
www.ite.com.tw IT8875F v0.1 www.iteusa.com itpm-pn-200 1106 specifications subject to change without notice by p.c. lin, 03/13/2001 1 features 1. features n pci interface - pci specification v2.1 compliant - supports 32-bit pci bus & up to 33 mhz pci bus frequency - supports perr# & serr# error reporting - supports delayed transaction n programmable pci address decoders - supports 6 programmable, size configurable, i/o and memory spaces - provides 5 positively decoded i/o blocks n compact bus interface - supports a compact bus structure to hook up an external i/o device - supports maximum 4 decoding chip selects n ieee 1284 parallel port - standard mode ? bi-directional spp compliant - enhanced mode ? epp v. 1.7 and v. 1.9 compliant - high speed mode ? ecp, ieee 1284 compliant - back-drive current reduction - printer power-on damage reduction n sm bus - compliant with system management bus specification r. 1.0 - supports single master mode - interfaced to serial e 2 prom n power-on serial bus configuration - power-on auto configuration through sm bus - patent pending on auto-start and auto-stop scheme n miscellanies - supports 24 mhz oscillator circuit n +3.3v pci i/f with +5v tolerant i/o buffers, +5v isa i/f and core power supply n package: 128-pin pqfp
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 3 general description 2. general description the IT8875F is a pci interface to a parallel port chip. the IT8875F ? s 32-bit pci bus interface is compliant with pci specification v2.1. the parallel port in IT8875F supports standard mode (spp), epp v.17 and v.19 and ecp mode. due to the variation of system platform, dma mode is not supported in IT8875F. the IT8875F also provides a compact bus structure to connect an external device. the compact bus structure facilitates the system engineers to hook an 8-bit external device by programming the intc base address register and positive decoding registers. overall, the IT8875F provides a simple solution to build a parallel port on pci bus. in addition, the IT8875F also integrates one sm bus (single master mode) which can be connected to a serial e 2 prom for automatic power-on configuration and providing customers with maximum design flexibility. the IT8875F is available in 128-pin pqfp package.
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 5 block diagram 3. block diagram pci slave pci configuration registers interrupt controller inta# isa bus data / control logic power_on configuring IT8875F (pci to parallel port chip) pci bus cs# decoder sm bus master external i/o devices sub_isa bus parallel port device serial e 2 prom central interface bus oscillator & clock dividers testing circuit 24 mhz crystal internal pci bus parallel port pio cycle conversion
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 7 pin configuration 4. pin configuration ad25 ad24 cbe3# idsel ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 cbe2# irdy# frame# trdy# devsel# stop# perr# serr# par ad14 ad13 ad12 ad11 ad10 ad8 ad9 ad15 vcc3 gnd ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 sda scl gnd vcc gnd sa2 sa1 sa0 rstdrv testin# ad27 ad26 sd7 sd6 sd5 vcc sd3 sd2 sd1 sd0 gnd slct pe busy ack# pd7 pd6 pd5 vcc pd4 pd3 pd2 pd1 pd0 slin# init# alfd# stb# perror# inta#/serirq isagnt# isareq# ad31 ad30 ad29 pcirst# pciclk cbe0# 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 31 32 33 34 35 36 37 38 59 60 61 62 63 64 104 105 106 107 108 103 72 71 70 69 68 67 66 65 IT8875F 128-pqfp ad28 cbe1# gnd ck24m ck24me gnd csa2# csa1# csa0# ior# iow# csa3# vcc gnd sd4 vcc gnd gnd gnd gnd gnd gnd gnd gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc3 vcc3 vcc3
www.ite.com.tw IT8875F v0.1 www.iteusa.com 8 it8 875f table 4 - 1 . pins listed in numeric order pin signal pin signal pin signal pin signal 1 vcc3 33 ad11 65 gnd 97 nc 2 ad28 34 ad10 66 gnd 98 gnd 3 ad27 35 ad9 67 gnd 99 gnd 4 ad26 36 ad8 68 gnd 100 gnd 5 ad25 37 gnd 69 nc 101 gnd 6 ad24 38 cbe0# 70 nc 102 gnd 7 cbe3# 39 vcc3 71 nc 103 slct 8 idsel 40 gnd 72 nc 104 pe 9 ad23 41 ad7 73 nc 105 busy 10 ad22 42 ad6 74 nc 106 ack# 11 ad21 43 ad5 75 nc 107 pd7 12 ad20 44 ad4 76 csa3# 108 pd6 13 vcc3 45 ad3 77 vcc 109 pd5 14 ad19 46 ad2 78 ck24me 110 vcc 15 ad18 47 ad1 79 ck24m 111 pd4 16 ad17 48 ad0 80 gnd 112 pd3 17 ad16 49 sda 81 csa2# 113 pd2 18 cbe2# 50 scl 82 csa1# 114 pd1 19 frame# 51 gnd 83 sd0 115 pd0 20 irdy# 52 nc 84 sd1 116 slin# 21 trdy# 53 nc 85 sd2 117 init# 22 devsel# 54 nc 86 sd3 118 alfd# 23 stop# 55 nc 87 vcc 119 stb# 24 perr# 56 vcc 88 sd4 120 perror# 25 serr# 57 gnd 89 gnd 121 inta#/serirq 26 vcc3 58 sa2 90 sd5 122 isagnt# 27 par 59 sa1 91 sd6 123 isareq# 28 cbe1# 60 sa0 92 sd7 124 ad31 29 ad15 61 rstdrv 93 csa0# 125 ad30 30 ad14 62 testin# 94 ior# 126 ad29 31 ad13 63 nc 95 iow# 127 pcirst# 32 ad12 64 nc 96 vcc 128 pciclk
www.ite.com.tw IT8875F v0.1 www.iteusa.com 9 it8 875f pin descriptions 5. IT8875F pin descriptions table 5 - 1 . pin descriptions of supplies signals pin(s) no. symbol attribute power description 56, 77 ,87, 96, 110 vcc pwr - +5v power supply. 1, 13, 26, 39 vcc3 pwr - +3.3v power supply. 37, 40, 51, 57, 65, 66, 67, 68, 80, 89, 98, 99, 100, 101, 102 gnd gnd - ground. table 5 - 2 . pin descriptions of pci bus interface signals pin(s) no. symbol attribute power description 124-126, 2-6, 9-12, 14-17, 29-36, 41-48 ad[31:0] i/o16 vcc3 pci multiplexed address / data 31 ? 0. 32-bit bi-directional address/data multiplexed lines. ad31 is the msb and ad0 is the lsb. the direction of these pins are defined below: phase bus master target address phase output input read data phase input output write data phase output input 7, 18, 28, 38 cbe[3:0]# i/o16 vcc3 command/byte enable 3 - 0 #. multiplexed bus command and byte enables. 22 devsel# i/o16 vcc3 device select #. when driven active low, the signal indicates the driving device has decoded its address as the target of the current access. this pin acts as an output pin when the IT8875F (including isa slave) is the slave of the pci bus cycle transaction. otherwise, it is an input pin. 21 trdy# i/o16 vcc3 target ready #. this signal indicates that the target of the current data phase of the transaction is ready to be completed. this pin acts as an output pin when the IT8875F (including isa slave) is the slave of the pci bus cycle transaction. otherwise, it is an input pin. 20 irdy# i/o16 vcc3 initiator ready #. this signal indicates that the initiator is ready to complete the current data phase of the transaction.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 10 it8 875f table 5 -2. pin descriptions of pci bus i nterface signals (cont ? d) pin(s) no. symbol attribute power description 19 frame# i/o16 vcc3 frame #. this signal is driven by the initiator to indicate the beginning and duration of a pci access. 8 idsel i vcc3 initialization device select. this signal is used as a chip select during pci configuration read / write transactions. 27 par i/o16 vcc3 parity. this signal is used for the even parity check on both ad[31:0] & cbe[3:0]# lines. the par input/output direction follows the ad[31:0] input/output direction. 24 perr# i/o16 vcc3 parity error #. this signal is used for reporting data parity errors during all pci transactions, except in a special cycle. perr# is an output when it detects a parity error in receiving data as a pci target. 25 serr# i/o16_od vcc3 system error #. this signal is used for reporting address parity errors, data parity errors on the special cycle command, or any other system error where the result will be catastrophic. (input for ic test only) 23 stop# i/o16 vcc3 stop #. this signal indicates that the current target is requesting the initiator to stop the current transaction. this pin acts as an output pin when the IT8875F (including isa slave) is the slave of the pci bus cycle transaction. otherwise, it is an input pin. 121 inta# / serirq i/o16_od vcc3 pci bus interrupt request a # / serialized irq. interrupt request a# of pci bus. serialized irq (for on board testing only). 123 isareq# i/o8 vcc3 pci bus request #. this request signal is asserted to request the host bridge. 122 isagnt# i vcc3 pci bus grant #. this acknowledge (grant) signal is asserted from the host bridge. 128 pciclk i vcc3 33 mhz pci clock. 127 pcirst# i vcc3 pci bus reset #. pcirst# is used to reset pci bus devices.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 11 it8 875f pin descriptions table 5 - 3 . pin descriptions of partial isa bus signals pin(s) no. symbol attribute power description 58-60 sa[2:0] i_sc_pu/o 8 vcc isa address 2 - 0. sa[2:0] are isa address outputs. they are also testing inputs. 83-86, 88, 90-92 sd[7:0] i_sc_pu/ o8 vcc isa data 7 - 0. 8-bit bi-directional data lines. sd7 is the msb. 94 ior# i_sc_pu/ o8 vcc i/o read #. active low output asserted by the cpu to read data or status information from the isa device. this pin acts as input when the chip is being tested. 95 iow# i_sc_pu/ o8 vcc i/o write #. active low output asserted by the cpu to write data or control information to the isa device. this pin acts as an input when the chip is being tested. 61 rstdrv i_sc_pu/ o8 vcc isa reset. a high level on this output resets the isa bus. this signal asynchronously terminates any activity and places the isa device in the reset state.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 12 it8 875f table 5 - 4 . pin descriptions of parallel port signals pin(s) no. symbol attribute power description 103 slct i_sc_pu vcc printer being selected indicator. the slct is the input status to indicate the printer is being selected to respond to the parallel port transaction. 104 pe i_sc_pu vcc printer paper end indicator. the pe is the input status to indicate the printer has run out of paper. 105 busy i_sc_pu vcc printer busy indicator. the busy is the input status to indicate the printer has a local operation in progress and can not accept data. 106 ack# i_sc_pu vcc printer acknowledge indicator#. the ack# is the input status to indicate the printer has already received a character and ready to accept another one. 120 perror# i_sc_pu vcc printer error#. printer error input for parallel port i/f. 116 slin# i_sc_pu/o 24 vcc printer slin #. printer selecting output for parallel port i/f. 117 init# i_sc_pu/o 24 vcc printer init#. printer initializing output for parallel port i/f. 118 alfd# i_sc_pu/o 24 vcc printer alfd#. printer auto line feed output for parallel port i/f. 119 stb# i_sc_pu/o 24 vcc printer stb#. printer strobe output for parallel port i/f. 107-109, 111-115 pd[7:0] i_sc_pu/o 24 vcc parallel port data bus: pd7~pd0. printer data bus for parallel port i/f.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 13 it8 875f pin descriptions table 5 - 5 . pin descriptions of miscellaneous signals pin(s) no. symbol attribute power description 49 sda i_sc_pu/o 4_od vcc serial bus data. system management bus data for serial e 2 prom. 50 scl i_sc_pu/o 4_od vcc serial bus clock. system management bus clock output for serial e 2 prom. (input for ic test only) 62 testin# i_pu vcc chip test mode. for chip testing only, and should be left unconnected or p/u. 78, 79 ck24me/ ck24m i/o_osc/ i_osc vcc 24 mhz oscillator. connected to 24 mhz crystal. 76, 81, 82, 93 csa[3:0]# i_sc_pu/o 4 vcc chip select group_a[3:0] #. chip select group_a[3-0] output which shares the same high base address. 52-55 nc - - not connected. 63-64 nc - - not connected. 69-75 nc - - not connected. 97 nc - - not connected. attributes: i: input i/o8: 8ma input/output i/o16: 16ma input/output i/o16_od: 16ma input/open drain output i_sc_pu: schmitt input with 50k pull down i_sc_pu/o8: 8 ma schmitt input with 50k pull up/output i_sc_pu/o24: 24 ma schmitt input with 50k pull up/output
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 15 power on strapping options 6. power on strapping options symbol pin # jumper description (p/up) inta#. csa0# 93 p/down serirq#. (p/up) enable sm bus boot rom configuration. it will set cfg_50h<4>, but will be auto- cleared when finishing download configure code. csa2# 81 p/down disable sm bus boot rom configuration.
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 17 system configuration 7. system configuration 7.1 overview the IT8875F is a pci to parallel port interface and provides a method to hook up an i/o device onto pci bus with a compact bus interface. the IT8875F ? s 32 ? bit pci bus interface is compliant with pci specification v2.1. the pci interface also supports positive decode space and 6 pci i/o or memory spaces. the device also contains one sm bus (single master mode) which can be connected to serial e 2 prom for automatic power-on configuration. the IT8875F also provides one pci interrupt pin and serial irq which can be selected during the power-on strapping. the IT8875F is available in 128-pin pqfp package. 7.2 features n pci interface - pci specification v2.1 compliant - supports 32-bit pci bus & up to 33 mhz pci bus frequency - supports perr# & serr# error reporting - supports delayed transaction n ieee 1284 parallel port - standard mode ? bi-directional spp compliant - enhanced mode ? epp v. 1.7 and v. 1.9 compliant - high speed mode ? ecp, only pio mode supported - back-drive current reduction - printer power-on damage reduction n compact external bus interface - supports only 8-bit i/o interface n programmable pci address decoders - supports programmable positive decode of pci cycles only - provides 5 positively decoded i/o blocks n sm bus - compliant with system management bus specification r. 1.0 - supports single master mode - interfaces to serial e 2 prom n power-on serial bus configuration - power-on auto configuration through sm bus - patent pending on auto-start and auto-stop scheme n serial irq - complies with serialized irq support for pci system r6.0 - supports both continuous and quiet modes - auto-detects start frame width and slot number n 4 chip selects - supports 8 bytes space
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 19 functional description 8. functional description the IT8875F provides a pci bus to parallel port interface and a compact bus structure used to connect an external device. there are some sub-function blocks in the IT8875F as described below: 8.1 pci slave interface the IT8875F pci slave interface provides some positively decode spaces: IT8875F pci configuration register spaces ? positively decode w/ medium devsel# speed on the type0 pci configuration cycle. the access space is described in section 9.2 access configuration registers on page 24 6 pci i/o or memory spaces. the space size and attribute of the address register depend on smb load value for the corresponding register. for size, when the bit is loaded with a ? 0 ? , it is read only, and hard wired to ? 0 ? : cfg_10h ~ cfg_24h five i/o positively decode spaces ? defined in IT8875F configuration registers: cfg_60h ~ cfg_70h. the IT8875F supports pci 2.1 delayed transaction feature which can be enabled / disabled by programming cfg_40h<21>. the benefit of delayed transaction is that the pci bus is still available and can be used by another pci master, even when there is an isa pio cycle in progress behind IT8875F. 8.2 pci parity the IT8875F, like other standard pci devices, can handle parity error and other errors. whenever the IT8875F detects address parity error, it is able to assert serr# if the serr# reporting mechanism is enabled in pci command/status register. 8.3 positively decode spaces the five positively decode i/o spaces can be programmed to claim the pci i/o cycle with fast / medium / slow / devsel# timing speed. 8.4 smb boot rom configuration in addition that the IT8875F configuration can be done by pci configuration cycles through system chipset, the IT8875F also offers an optional configuration method via the system management bus (smb, similar to i 2 c bus) boot rom. as the current version of IT8875F only supports single master mode, users are prohibited to connect the IT8875F smb interface to another system smb bus. only serial e 2 prom can be connected, and the preset slave address is 1010000b. the serial e 2 prom data is grouped by each five bytes into the 1 st byte, which serves as an index to indicate which pci configuration register is. the other 4 bytes are the 32-bit data, which will be written to the indexed register.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 20 it8 875f smb rom data format in serial e 2 prom is illustrated below: rom address rom data IT8875F operation top 5n index = aah stop 5m+4 data cfg_50h<31:24> 5m+3 data cfg_50h<23:16> 5m+2 data cfg_50h<15:8> 5m+1 data cfg_50h<7:0> 5m index = 50h cfg_50h 6 data cfg_xxh<7:0> 5 index = xxh cfg_xxh 4 data cfg_??h<31:24> 3 data cfg_??h<23:16> 2 data cfg_??h<15:8> 1 data cfg_??h<7:0> 0 index = ??h cfg_??h whether the chip will execute smb boot rom configuring sequence or not is determined by one power-on- strap setting. please refer to the table in section 6 power on strapping options on page 15. if smb boot rom configuration is enabled, the IT8875F will then set the smb_in_progress status bit (cfg_40h<18>) on page 32 and begin to issue the i 2 c sequential read operation. it writes to pci configuration registers after it has finished reading every five bytes from smb rom. if it reads an index value as aa hex , it will then stop i 2 c sequential read operation and clear the smb_in_progress status bit. the system bios can monitor the status bit to see if smb is in progress before bios can decide to enable some computer system sub-functions. conversely, if smb boot rom configuration is disabled in power-on-strap setting, the IT8875F will then clear the smb_in_progress status bit, and no i 2 c sequential read operation occurs. for instance, if users intend to claim one i/o space of 02ac h ~ 02ad h (2byte size) for a special isa card (or users try to hook up the isa device to pci bus), a serial e 2 prom can be programmed. the resulted data are listed on the next page:
www.ite.com.tw IT8875F v0.1 www.iteusa.com 21 functional description serial e 2 prom address data IT8875F configuration register top ~ 6 xx h 5 aa h IT8875F smb i/f stop 4 c1 h cfg_64h<31:24> medium devsel#, 2byte size 3 00 h cfg_64h<23:16> = reserved 2 02 h 1 ac h cfg_64h<15:0> = 02ac h 0 64 h index 64 h => cfg_64h in the example above, the IT8875F smb configuration block will write the 32-bit data of c10002ac h to cfg_64h when it finishes reading bytes 0~4 of serial e 2 prom. after it receives an aa h in the rom position of 5xn (i.e. address of 5 d , 10 d , 15 d , .. etc.), the smb i/f stops fetching more data and clears the smb_in_progress status bit. for detailed smb configuration operation, please refer to the ? IT8875F smb configuration programming guide ? . the smb boot configuring mechanism is patent pending. 8.5 4 chip selects IT8875F provides 4 chip selects for application usage. it could be 8 bytes for each space. please refer to page 40 for more details. 8.6 parallel port - standard mode ? bi-directional spp compliant - enhanced mode ? epp v. 1.7 and v. 1.9 compliant - high speed mode ? ecp, only pio mode supported - back-drive current reduction - printer power-on damage reduction
www.ite.com.tw IT8875F v0.1 www.iteusa.com 22
www.ite.com.tw IT8875F v0.1 www.iteusa.com 23 register descriptions 9. register descriptions 9.1 configuration register map the IT8875F pci header configuration register set complies with type 00h configuration space header described in the pci specification r. 2.1. table 9 - 1 . IT8875F configuration register map 31 16 15 00 index device id (8875h) vendor id (1283h) 00h status command 04h base class code (07h) sub-class code(00/01) programming i/f (02h) revision id (01h) 08h reserved (00h) header type (00h) latency timer (00h) cache line size (00h) 0ch pci space_0 base address 10h pci space_1 base address 14h pci space_2 base address 18h pci space_3 base address 1ch pci space_4 base address 20h pci space_5 base address 24h reserved (00000000h) 28h sub-system device id (0000h) sub-system vendor id (0000h) 2ch reserved 30h reserved (00000000h) 34~3bh reserved (0000h) interrupt pin interrupt line 3ch global control _ 1 register 40h global control _ 2 register 44h reserved 48h reserved 4ch pci space_1/0 remap register 50h pci space_3/2 remap register 54h pci space_5/4 remap register 58h reserved 5ch positively decoded i/o_space_0 register 60h positively decoded i/o_space_1 register 64h positively decoded i/o_space_2 register 68h positively decoded i/o_space_3 register 6ch positively decoded i/o_space_4 register 70h reserved 74h intc base address register 78h reserved 7ch internal parallel port base address register 80h reserved 84h external devices base address register 1 88h reserved 8ch reserved 90h reserved 94h reserved 98h miscellaneous control register (miscr) 9ch reserved a0h~ffh
www.ite.com.tw IT8875F v0.1 www.iteusa.com 24 it8 875f 9.2 access configuration registers the IT8875F will respond to all pci bus configuration cycles when the idsel input is asserted high. address bits 1-0 of the configuration cycle are both ? 0 ? , and address bits 10-8 correspond to internal functions. the type0 configuration address format is as follows: ad31-11 ad10-8 ad7-2 ad1-0 cbe3-0# only one asserted to active idsel function select, IT8875F only responds to function = 000b register select, to select one double- word register configuration type, IT8875F only responds to type = 00b byte select, to select one or more bytes in selected double-word register the configuration registers can be accessed as byte, or word (16 bits) or double-word (32 bits) quantities or any byte combination. in all of these accesses, only byte enables are used, ad[1:0] is always 00b when accessing the configuration registers. all multi-byte fields use ? little-endian ? ordering (that is, lower addresses contain the least significant parts of the fields). registers that are marked ? reserved ? will be decoded and return zeros when read. all bits defined as ? reserved ? within IT8875F ? s pci configuration registers will be read as zero and will be unaffected by writes, unless specifically documented otherwise. the software can use the pci configuration mechanism one to read or write the IT8875F pci configuration register space. the pci configuration mechanism one utilizes two 32-bit i/o ports located at addresses 0cf8h and 0cfch. these two ports are: index port: 32-bit in bit width, occupying i/o address 0cf8h through 0cfbh. data port: 32-bit in bit width, occupying i/o address 0cfch through 0cffh. 0 4g pci i/o address space 0cf8h-0cfbh 0cfch-0cffh data 00h 01h 02h 03h 04h 05h 06h 07h fch fdh feh ffh 08h 09h 0ah 0bh index=0h index=1h index=2h index index=3fh function=0 00h 01h 02h 03h 04h 05h 06h 07h fch fdh feh ffh 08h 09h 0ah 0bh function=1 00h 01h 02h 03h 04h 05h 06h 07h fch fdh feh ffh 08h 09h 0ah 0bh function=7 host chipset idsel figure 9 - 1 . pci configuration register structure
www.ite.com.tw IT8875F v0.1 www.iteusa.com 25 register descriptions accessing any pci configuration register is a two-step process: step 1: perform i/o writes of the bus number, physical device number, function number, and register index number to the pci configuration mechanism one index port. (the motherboard chipset will decode the bus number, device number and then generate the idsel signal to select the device. the device then decodes the function number to select which bank of the register is to be accessed and decodes the register index number to select which double-word register will be accessed.) step 2: perform an i /o read from or write to the pci configuration mechanism one data port. the pci configuration mechanism one index & data port formats are illustrated below: 1 reserved bus number device number function number register index number 0 0 31 30 24 23 16 15 11 10 8 7 2 1 0 enable config. space mapping pci configuartion mechanism one index port format maximum of 256 buses maximum of 32 devices maximum of 8 functions maximum of 64 double-word (8 bits) (5 bits) (3 bits) (6 bits) pci configuration mechanism one (msb) byte 3 byte 2 31 24 23 16 15 8 7 0 pci configuartion mechanism one data port format byte 1 byte 0 (lsb) figure 9 - 2 . pci configuration access mechanism #1
www.ite.com.tw IT8875F v0.1 www.iteusa.com 26 it8 875f 9.3 configuration register descriptions 9.3.1 device/vendor id register (idr) ? offset 00h bit r/w default description 31 - 16 r/l 8875h device id (did) the device id register contains the device identification number for this chip - IT8875F. 15 - 0 r/l 1283h vendor id (vid) the vendor id register contains the vendor identification number for ite. 9.3.2 status / command register (scr) ? offset 04h bit r/w default description 31 r/w1c 0b set by IT8875F whenever it detects a parity error on pci bus. 30 r/w1c 0b set by IT8875F whenever it asserts serr#. 29 ro 0b reserved 28 ro 0b reserved 27 r/w1c 0b set by IT8875F whenever it, as a target, terminates a transaction by signaling a target abort. 26 - 25 r/l 01b medium devsel# timing for IT8875F as a target to respond to an access on pci bus. 24 r/w1c 0b set by IT8875F when two conditions are met: 1) asserting perr# itself or observing perr# being asserted; 2) cfg_04h<6> is set. 23 ro 1b fast back-to-back capability (when IT8875F acts as a target). 22 - 16 ro all zero reserved 15 - 10 ro all zero reserved 9 ro 0b fast back-to-back control IT8875F will not perform fbtb access to the target on pci bus. 8 r/w/l 0b serr# drives low enable a value of 1 enables IT8875F to drive serr#. a value of 0 disables serr# signal. (cfg_04_8) 7 ro 0b ad bus stepping IT8875F does not perform ad stepping. 6 r/w/l 0b parity error response when the bit is 0, IT8875F will ignore any parity error, which is detected on pci bus interface. (cfg_04_6) 5 - 2 ro 0000b reserved 1 r/w/l 0b downstream memory transaction enabling (mem_en) 0 r/w/l 0b downstream i/o transaction enabling (io_en)
www.ite.com.tw IT8875F v0.1 www.iteusa.com 27 register descriptions 9.3.3 class code/ revision id register (ccridr) ? offset 08h bit r/w default description 31 - 24 r/l 07h base class code (bcc) this register contains the base class code for IT8875F. this base class code is 07h, indicating it is a ? simple communication device ? . 23 - 16 r/l 00h sub-class code (scc) this register contains the sub-class code for IT8875F. this sub-class code is 00h, indicating it is an ? serial port controller. ? when the sub- class code is 01h, it indicates it is an ? parallel port controller. ? 15 - 8 r/l 02h programming interface (pif) the pif byte of the class code register indicates it is spp or ecp, please refer to pci spec. 2.1, appendix d. 7 - 0 r/l 01h revision identification (rid) this register contains the device revision number for IT8875F device. 9.3.4 header type/ mlt/ cache line size register (hmcr) ? offset 0ch bit r/w default description 31 - 24 ro 00h reserved 23 - 16 ro 00h header type (htr) this register identifies the header layout of the configuration space. 15 - 8 ro 00h reserved 7 - 0 ro 00h cache line size (cls) this register specifies the system cache-line size in the unit of 32-bit words.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 28 it8 875f 9.3.5 pci space_0 base address register (ps0bar) ? offset 10h bit r/w default description 31 - 4 r/w/l 0000000h pci space_0 base address bits 31 - 4 (ps0bar[31:4] ) this pci space_0 base address, high bits are r/w/l for allocating pci resources; low bits are read only as 0 for showing space size information. 3 r/w/l 0b pci space_0 base address bit 3 (ps0bar[3] ) when ps0bar<0>=0, this bit is memory prefetchable setting. when ps0bar<0>=1, this bit is i/o space base address a[3]. 2 r/w/l 0b pci space_0 base address bit 2 (ps0bar[2] ) when ps0bar<0>=0, this bit is must be written with 0. when ps0bar<0>=1, this bit is i/o space base address a[2]. 1 r/w/l 0b pci space_0 base address bit 1 (ps0bar[1] ) when ps0bar[0]>=0, this bit is memory addressing in 32-bit (set to 0) or below 1mb (set to 1). when ps0bar[0]>=1, this bit must be written with 0. 0 r/l 1b pci space_0 attribute (ps0bar[0]) set to 0 for memory space; set to 1 for i/o space. 9.3.6 pci space_1 base address register (ps1bar) ? offset 14h bit r/w default description 31 - 4 r/w/l 0000000h pci space_1 base address bits 31 - 4 (ps1bar[31:4] ) this pci space_1 base address, high bits are r/w/l for allocating pci resources; low bits are read only as 0 for showing space size information. 3 r/w/l 0b pci space_1 base address bit 3 (ps1bar[3] ) when ps1bar<0>=0, this bit is memory prefetchable setting. when ps1bar<0>=1, this bit is i/o space base address a[3]. 2 r/w/l 0b pci space_1 base address bit 2 (ps1bar[2] ) when ps1bar<0>=0, this bit is must be written with 0. when ps1bar<0>=1, this bit is i/o space base address a[2]. 1 r/w/l 0b pci space_1 base address bit 1 (ps1bar[1] ) when ps1bar[0]>=0, this bit is memory addressing in 32-bit (set to 0) or below 1mb (set to 1). when ps1bar[0]>=1, this bit must be written with 0. 0 r/l 1b pci space_1 attribute (ps1bar[0]) set to 0 for memory space; set to 1 for i/o space.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 29 register descriptions 9.3.7 pci space_2 base address register (ps2bar) ? offset 18h bit r/w default description 31 - 4 r/w/l 0000000h pci space_2 base address bits 31 - 4 (ps2bar[31:4] ) this pci space_2 base address, high bits are r/w/l for allocating pci resources; low bits are read only as 0 for showing space size information. 3 r/w/l 0b pci space_2 base address bit 3 (ps2bar[3] ) when ps2bar<0>=0, this bit is memory prefetchable setting. when ps2bar<0>=1, this bit is i/o space base address a[3]. 2 r/w/l 0b pci space_2 base address bit 2 (ps2bar[2] ) when ps2bar<0>=0, this bit is must be written with 0. when ps2bar<0>=1, this bit is i/o space base address a[2]. 1 r/w/l 0b pci space_2 base address bit 1 (ps2bar[1] ) when ps2bar[0]>=0, this bit is memory addressing in 32-bit (set to 0) or below 1mb (set to 1). when ps2bar[0]>=1, this bit must be written with 0. 0 r/l 1b pci space_2 attribute (ps2bar[0]) set to 0 for memory space; set to 1 for i/o space. 9.3.8 pci space_3 base address register (ps3bar) ? offset 1ch bit r/w default description 31 - 4 r/w/l 0000000h pci space_3 base address bits 31 - 4 (ps3bar[31:4] ) this pci space_3 base address, high bits are r/w/l for allocating pci resources; low bits are read only as 0 for showing space size information. 3 r/w/l 0b pci space_3 base address bit 3 (ps3bar[3] ) when ps3bar<0>=0, this bit is memory prefetchable setting. when ps3bar<0>=1, this bit is i/o space base address a[3]. 2 r/w/l 0b pci space_3 base address bit 2 (ps3bar[2] ) when ps3bar<0>=0, this bit is must be written with 0. when ps3bar<0>=1, this bit is i/o space base address a[2]. 1 r/w/l 0b pci space_3 base address bit 1 (ps3bar[1] ) when ps3bar[0]>=0, this bit is memory addressing in 32-bit (set to 0) or below 1mb (set to 1). when ps3bar[0]>=1, this bit must be written with 0. 0 r/l 1b pci space_3 attribute (ps3bar[0]) set to 0 for memory space; set to 1 for i/o space.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 30 it8 875f 9.3.9 pci space_4 base address register (ps4bar) ? offset 20h bit r/w default description 31 - 4 r/w/l 0000000h pci space_4 base address bits 31 - 4 (ps4bar[31:4] ) this pci space_4 base address, high bits are r/w/l for allocating pci resources; low bits are read only as 0 for showing space size information. 3 r/w/l 0b pci space_4 base address bit 3 (ps4bar[3] ) when ps4bar<0>=0, this bit is memory prefetchable setting. when ps4bar<0>=1, this bit is i/o space base address a[3]. 2 r/w/l 0b pci space_4 base address bit 2 (ps4bar[2] ) when ps4bar<0>=0, this bit is must be written with 0. when ps4bar<0>=1, this bit is i/o space base address a[2]. 1 r/w/l 0b pci space_4 base address bit 1 (ps4bar[1] ) when ps4bar[0]>=0, this bit is memory addressing in 32-bit (set to 0) or below 1mb (set to 1); when ps4bar[0]>=1, this bit must be written with 0. 0 r/l 1b pci space_4 attribute (ps4bar[0]) set to 0 for memory space; set to 1 for i/o space. 9.3.10 pci space_5 base address register (ps5bar) ? offset 24h bit r/w default description 31 - 4 r/w/l 0000000h pci space_5 base address bits 31 - 4 (ps5bar[31:4] ) this pci space_5 base address, high bits are r/w/l for allocating pci resources; low bits are read only as 0 for showing space size information. 3 r/w/l 0b pci space_5 base address bit 3 (ps5bar[3] ) when ps5bar<0>=0, this bit is memory prefetchable setting. when ps5bar<0>=1, this bit is i/o space base address a[3]. 2 r/w/l 0b pci space_5 base address bit 2 (ps5bar[2] ) when ps5bar<0>=0, this bit is must be written with 0. when ps5bar<0>=1, this bit is i/o space base address a[2]. 1 r/w/l 0b pci space_5 base address bit 1 (ps5bar[1] ) when ps5bar[0]>=0, this bit is memory addressing in 32-bit (set to 0) or below 1mb (set to 1). when ps5bar[0]>=1, this bit must be written with 0. 0 r/l 1b pci space_5 attribute (ps5bar[0]) set to 0 for memory space; set to 1 for i/o space.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 31 register descriptions 9.3.11 sub-system device id / sub-system vendor id ? offset 2ch bit r/w default description 31 ? 16 r/gw 1 / l 0000h sub-system device id (sdid) this value is used to identify a particular sub-system. this register along with svid register is used to uniquely identify the add-in board or sub- system where the pci device resides. 15 ? 0 r/gw/l 0000h sub-system vendor id (svid) this value is used to identify the vendor of the sub-system. sub-system vendor ids can be obtained from the pci-sig and are used to identify the vendor of the add-in board or sub-system. 9.3.12 interrupt pin/line register (intr) ? offset 3ch bit r/w default description 31 - 16 ro 0000h reserved 15 - 8 r/l 00h/01h interrupt pin (intpin) if serirq pin function is selected, these bits default are then read as 00h; otherwise, read as 01h. 7 - 0 r/w/l 0ah interrupt line (intline) interrupt routine number of 8259x2. 1 gw = gated write (controlled by gc1r<22>)
www.ite.com.tw IT8875F v0.1 www.iteusa.com 32 it8 875f 9.3.13 global control_1 register (gc1r) ? offset 40h bit r/w default description 31 r/w/l 0b test smb interface ( test_smb) reserved for ic test only. 30 - 23 r/w/l all 0 reserved 22 r/w/l 0b allow pci configure write operation to change the content of sub- system device/vendor id register ( sub_id_w_en) 0: disabled, only smb_rom configuring can update it. 1: enabled. it is generally provided for optional device bios to change sub-system id for its device. 21 r/w/l 0b enable delayed transaction in pio cycle ( delay_x_en) 0: disabled. 1: enabled. 20 ro 1b reserved 19 r/w/l reset strap value of csa1# reserved 18 ro reset strap value of csa2# smb_in_progress ( sm_cfg_cycle) it shows the status of sm bus boot rom being in progress. if csa2# is sampled high during reset, this bit will be set to 1, and the sm bus boot rom configuration will be initiated. once the configuration is finished (get index= aah), this bit will be cleared automatically. 17 r/w/l 0b enable i/o byte lane error to serr# (serr_iobe_en) enable checking pci i/o cycle byte lane error and report to serr#. 0: disabled. 1: enabled. 16 r/w1c 0b i/o byte error status (iobe_status) read 1 as the pci i/o cycle byte lane error occurred. write 1 to clear. 15 r/w/l 0b enable discard overflow report to serr# ( serr_discard_en) 0: disabled. 1: enabled. 14 r/w1c 0b read 1 as the pci target interface can not receive the same retried transaction more than the time (overflow) defined in gc1r<13:8>. write 1 to clear. 13 - 8 r/w/l 3fh discard timer ( discard_timer[5:0]) if the pci master still does not repeat the same transaction when timer expired (value x256 pci clocks) for the pci target interface that issued the retry cycle, the pci target interface will then stop waiting and set status bit (gc1r<14>). 00h: never expire; 01h: 256t; ffh: 255*256t. 7 r/w/l 0b enable retry overflow report to serr# ( serr_retry_en) 0: disabled. 1: enabled. 6 r/w1c 0b read 1 as the pci master interface can not complete its transaction within the time (overflow) defined in gc1r<5:0>. write 1 to clear. 5 - 0 r/w/l 3fh retry timer ( retry_timer[5:0]) pci master interface repeats retried transactions and if the retry counts exceed the retry timer value (x 8 times), the pci master interface will then give up more retry and set status bit (cfg_54h<6>). 00h:not check retry; 01h: 8 times; ffh: 255*8 times.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 33 register descriptions 9.3.14 global control_2 register (gc2r) ? offset 44h bit r/w default description 31 r/w/l reset strap value of csa0# pin # 121 function select (inta_sel) 0: serirq. 1: inta#. 30-20 r/w/l 6bfh reserved 19 ? 16 ro 0000b reserved 15 - 14 ro 10b reserved 13 - 12 r/w/l 00b 8-bit i/o access recovery time (recovery_8[1:0]) 00b: 3.5 bclk; 01b: 5.5 bclk; 10b: 7.5 bclk: 11b: 11.5 bclk. 11 r/w/l 1b 24m oscillator enable control (osc_en) 1: enabled. 0: disabled. this oscillator provides clocks for two internal uarts. 10 r/w/l 1b 24m oscillator pad feedback resistor enable control (osc_r_en_) 0: enabled. 1: disabled. 9 - 8 ro 11b reserved 7 - 6 r/w/l 11b wait state control of external i/o devices (ws_xio[1:0]) 00b: 3t (no wait state); 01b: 4t; 10b: 5t; 11b: 6t (standard isa 8-bit i/o). 5 - 4 ro 00b reserved 3 - 2 r/w/l 00b wait state control of internal parallel port controller (ws_ipp[1:0]) 00b: 3t (no wait state); 01b: 4t; 10b: 5t; 11b: 6t (standard isa 8-bit i/o). 1 - 0 ro 00b reserved
www.ite.com.tw IT8875F v0.1 www.iteusa.com 34 it8 875f 9.3.15 pci space_1/0 remap register (rmp10r) ? offset 50h bit r/w default description 31 - 17 r/w/l remap pci space_1 (rmp1[15:1]) if pci space_1<0> is: 0: access to the memory space defined in pci space_1 will be remapped to the space of {a[31:20]=ignore, a[19:6]=rmp1[15:2], a[5:0]= same} if the space claimed is not greater than 64 bytes ; otherwise {a[31:20]=ignore, a[19:(size_bit +1)]=rmp1[15: (size_bit ? 3)], a[size_bit:0]= same} where the size_bit depends on the pci space_1 size. 1: access to the i/o space defined in pci space_1 will be remapped to the space of {a[31:16]=ignore, a[15:(size_bit+1)]=rmp1[15:(size_bit+1)], a[size_bit:0]=same} where the size_bit depends on the pci space_1 size. 16 r/w/l 0000h enabl e remap pci space_1 (rmp1_en): 0: disabl e remapping . 1: enabl e remapping . 15 - 1 r/w/l remap pci space_0 (rmp0[15:1]). if pci space_0<0> is: 0: access to the memory space defined in pci space_0 will be remapped to the space of {a[31:20]=ignore, a[19:6]=rmp1[15:2], a[5:0]= same} if the space claimed is not greater than 64 bytes ; otherwise {a[31:20]=ignore, a[19:(size_bit +1)]=rmp1[15: (size_bit ? 3)], a[size_bit:0]= same} where the size_bit depends on the pci space_10 size. 1: access to the i/o space defined in pci space_0 will be remapped to the space of {a[31:16]=ignore, a[15:(size_bit+1)]=rmp0[15:(size_bit+1)], a[size_bit:0]=same} where the size_bit depends on the pci space_0 size. 0 r/w/l 0000h enabl e remap pci space_0 (rmp0_en) 0: disabl e remapping . 1: enabl e remapping .
www.ite.com.tw IT8875F v0.1 www.iteusa.com 35 register descriptions 9.3.16 pci space_3/2 remap register (rmp32r) ? offset 54h bit r/w default description 31 - 17 r/w/l 0000h remap pci space_3 (rmp3[15:1]) if pci space_3<0> is: 0: access to the memory space defined in pci space_3 will be remapped to the space of {a[31:20]=ignore, a[19:6]=rmp1[15:2], a[5:0]= same} if the space claimed is not greater than 64 bytes; otherwise {a[31:20]=ignore, a[19:(size_bit +1)]=rmp1[15: (size_bit ? 3)], a[size_bit:0]= same} where the size_bit depends on the pci space_3 size. 1: access to the i/o space defined in pci space_3 will be remapped to the space of {a[31:16]=ignore, a[15:1]=rmp3[15:1], a[size_bit:0]=same} where the size_bit depends on the pci space_3 size. 16 r/w/l enable remap pci space_3 (rmp3_en) 0: disable remapping. 1: enable remapping. 15 - 1 r/w/l remap pci space_2 (rmp2[15:1]) if pci space_2<0> is: 0: access to the memory space defined in pci space_2 will be remapped to the space of {a[31:20]=ignore, a[19:6]=rmp1[15:2], a[5:0]= same} if the space claimed is not greater than 64 bytes; otherwise {a[31:20]=ignore, a[19:(size_bit +1)]=rmp1[15: (size_bit ? 3)], a[size_bit:0]= same} where the size_bit depends on the pci space_2 size. 1: access to the i/o space defined in pci space_2 will be remapped to the space of {a[31:16]=ignore, a[15:1]=rmp2[15:1], a[size_bit:0]=same} where the size_bit depends on the pci space_2 size. 0 r/w/l 0000h enable remap pci space_2 (rmp2_en) 0: disable remapping. 1: enable remapping.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 36 it8 875f 9.3.17 pci space_5/4 remap register (rmp54r) ? offset 58h bit r/w default description 31 - 17 r/w/l remap pci space_5 (rmp5[15:1]) if pci space_5<0> is: 0: access to the memory space defined in pci space_5 will be remapped to the space of {a[31:20]=ignore, a[19:6]=rmp1[15:2], a[5:0]= same} if the space claimed is not greater than 64 bytes; otherwise {a[31:20]=ignore, a[19:(size_bit +1)]=rmp1[15: (size_bit ? 3)], a[size_bit:0]= same} where the size_bit depends on the pci space_5 size. 1: access to the i/o space defined in pci space_5 will be remapped to the space of {a[31:16]=ignore, a[15:1]=rmp5[15:1], a[size_bit:0]=same} where the size_bit depends on the pci space_5 size. 16 r/w/l 0000h enable remap pci space_5 (rmp5_en) 0: disable remapping. 1: enable rem apping. 15 - 1 r/w/l remap pci space_4 (rmp4[15:1]) if pci space_4<0> is: 0: access to the memory space defined in pci space_4 will be remapped to the space of {a[31:20]=ignore, a[19:6]=rmp1[15:2], a[5:0]= same} if the space claimed is not greater than 64 bytes; otherwise {a[31:20]=ignore, a[19:(size_bit +1)]=rmp1[15: (size_bit ? 3)], a[size_bit:0]= same} where the size_bit depends on the pci space_4 size. 1: access to the i/o space defined in pci space_4 will be remapped to the space of {a[31:16]=ignore, a[15:1]=rmp4[15:1], a[size_bit:0]=same} where the size_bit depends on the pci space_4 size. 0 r/w/l 0000h enable remap pci space_4 (rmp4_en) 0: disable remapping. 1: enable remapping.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 37 register descriptions 9.3.18 positively decoded i/o_space_0 register (posio0r) ? offset 60h bit r/w default description 31 r/w/l 0b i/o_space_0 enable (io_0_en) 0: no response. 1: IT8875F will respond to i/o_space_0. 30 - 29 r/w/l 00b decoding speed for i/o_space_0 (io_0_speed[1:0]) 00b: reserved; 10b: medium speed; 01b: slow speed; 11b: fast speed. 28 r/w/l 0b alias enable for i/o_space_0 (alias_0_en) 0: fully decode. 1: don ? t care a[15:10]. 27 ro 0b reserved 26 - 24 r/w/l 000b i/o_space_0 size (io_0_size[2:0]) 000b: 1 bytes; 010b: 4 bytes; 100b: 16 bytes; 110b: 64 bytes; 001b: 2 bytes; 011b: 8 bytes; 101b: 32 bytes; 111b: 128 bytes. 23 - 16 ro 00h reserved 15 - 0 r/w/l 0000h base address of i/o_space_0 (io_0_ba[15:0]) a[15:0], with a[31:16]=0000h. 9.3.19 positively decoded i/o_space_1 register (posio1r) ? offset 64h bit r/w default description 31 r/w/l 0b i/o_space_1 enable (io_1_en) 0: no response. 1: IT8875F will respond to i/o_space_1. 30 - 29 r/w/l 00b decoding speed for i/o_space_1 (io_1_speed[1:0]) 00b: reserved; 10b: medium speed; 01b: slow speed; 11b: fast speed. 28 r/w/l 0b alias enable for i/o_space_1 (alias_1_en) 0: fully decode. 1: don ? t care a[15:10]. 27 ro 0b reserved 26 - 24 r/w/l 000b i/o_space_1 size (io_1_size[2:0]) 000b: 1 bytes; 010b: 4 bytes; 100b: 16 bytes; 110b: 64 bytes; 001b: 2 bytes; 011b: 8 bytes; 1 01b: 32 bytes; 111b: 128 bytes. 23 - 16 ro 00h reserved 15 - 0 r/w/l 0000h base address of i/o_space_1 (io_1_ba[15:0]) a[15:0], with a[31:16]=0000h.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 38 it8 875f 9.3.20 positively decoded i/o_space_2 register (posio2r) ? offset 68h bit r/w default description 31 r/w/l 0b i/o_space_2 enable (io_2_en) 0: no response. 1: IT8875F will respond to i/o_space_2. 30 - 29 r/w/l 00b decoding speed for i/o_space_2 (io_2_speed[1:0]) 00b: reserved; 10b: medium speed; 01b: slow speed; 11b: fast speed. 28 r/w/l 0b alias enable for i/o_space_2 (alias_2_en) 0: fully decode. 1: don ? t care a[15:10]. 27 ro 0b reserved 26 ? 24 r/w/l 000b i/o_space_2 size (io_2_size[2:0]) 000b: 1 bytes; 010b: 4 bytes; 100b: 16 bytes; 110b: 64 bytes; 001b: 2 bytes; 011b: 8 bytes; 101b: 32 bytes; 111b: 128 bytes. 23 ? 16 ro 00h reserved 15 ? 0 r/w/l 0000h base address of i/o_space_2 (io_2_ba[15:0]) a[15:0], with a[31:16]=0000h. 9.3.21 positively decoded i/o_space_3 register (posio3r) ? offset 6ch bit r/w default description 31 r/w/l 0b i/o_space_3 enable (io_3_en) 0: no response. 1: IT8875F will respond to i/o_space_3. 30 - 29 r/w/l 00b decoding speed for i/o_space_3 (io_3_speed[1:0]) 00b: reserved; 10b: medium speed; 01b: slow speed; 11b: fast speed. 28 r/w/l 0b alias enable for i/o_space_3 (alias_3_en) 0: fully decode. 1: don ? t care a[15:10]. 27 ro 0b reserved 26 - 24 r/w/l 000b i/o_space_3 size (io_3_size[2:0]) 000b: 1 bytes; 010b: 4 bytes; 100b: 16 bytes; 110b: 64 bytes; 001b: 2 bytes; 011b: 8 bytes; 101b: 32 bytes; 111b: 128 bytes. 23 - 16 ro 00h reserved 15 - 0 r/w/l 0000h base address of i/o_space_3 (io_3_ba[15:0]) a[15:0], with a[31:16]=0000h.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 39 register descriptions 9.3.22 positively decoded i/o_space_4 register (posio4r) ? offset 70h bit r/w default description 31 r/w/l 0b i/o_space_4 enable (io_4_en) 0: no response. 1: IT8875F will respond to io_space_4. 30 - 29 r/w/l 00b decoding speed for i/o_space_4 (io_4_speed[1:0]) 00b: reserved; 10b: medium speed; 01b: slow speed; 11b: fast speed. 28 r/w/l 0b alias enable for i/o_space_4 (alias_4_en) 0: fully decode. 1: don ? t care a[15:10]. 27 ro 0b reserved 26 - 24 r/w/l 000b i/o_space_4 size (io_4_size[2:0]) 000b: 1 bytes; 010b: 4 bytes; 100b: 16 bytes; 110b: 64 bytes; 001b: 2 bytes; 011b: 8 bytes; 101b: 32 bytes; 111b: 128 bytes. 23 - 16 ro 00h reserved 15 - 0 r/w/l 0000h base address of i/o_space_4 (io_4_ba[15:0]) a[15:0], with a[31:16]=0000h.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 40 it8 875f 9.3.23 intc base address register (intcbar) ? offset 78h bit r/w default description 31 - 16 - - reserved 15 - 0 r/w/l 02a0h intc base address (intc_ba[15:0]) this value specif ies the intc base address (16-bytes space). 9.3.24 internal parallel port base address register (ippbar) ? offset 80h bit r/w default description 31 - 16 r/w/l 0778h internal parallel port base address for ecp mode (ipph_ba[15:0]) the last two bits are not used. 15 - 0 r/w/l 0378h internal parallel port base address for spp/epp mode (ippl_ba[15:0]) the last two bits are not used. 9.3.25 external devices base address register 1 (xdba1r) ? offset 88h bit r/w default description 31 - 16 ro 01a0h reserved 15 - 0 r/w/l 0180h external csa[3:0]# base address(csa_ba[15:0]) each one of csa[3:0]# spaces is 8 bytes, and the csa_ba[2:0] are not used in address comparator. the csa_ba[0] is recommended to set to 0. active signal address region csa[0]# csa_ba[15:0] to csa_ba[15:0]+7h csa[1]# csa_ba[15:0]+8h to csa_ba[15:0]+15h csa[2]# csa_ba[15:0]+16h to csa_ba[15:0]+23h csa[3]# csa_ba[15:0]+24h to csa_ba[15:0]+31h
www.ite.com.tw IT8875F v0.1 www.iteusa.com 41 register descriptions 9.3.26 miscellaneous control register (miscr) ? offset 9ch bit r/w default description 31 ? 30 r/w/l 11b internal parallel port operation mode (ipp_mode[1:0]) 00: spp; 01: spp & epp 10: spp & ecp 11: spp, epp & ecp 29 ? 27 ro 011b reserved 26 - 24 ro 001b reserved 23 - 22 ro 00b reserved 21 r/w/l 0b internal parallel port function enable control (ipp_en) 0: disabled. 1: enabled. 20 r/w/l 0 writes to auto addressing enable control (wtaa_en) 0: disabled. 1: enabled. if this bit is enabled, it8875 would allow pci configuration read/write to configuration space address 10h, 14h, 18h, 1ch, 20h, 24h, 30h to control the size registers corresponding to the normal base address register (if this bit is disabled). if this bit is 1, it indicates the corresponding base address register is read/write; otherwise it is read only. if this bit is disabled, pci configuration read/write operations will access the configuration space address 10h, 14h, 18h, 1ch, 20h, 24h, 30h to read/write the real pci base address registers. this bit is for ic verification usage only, and is not intended for the real application. 19 - 16 ro 0101b reserved 15 - 12 ro 0100b reserved 11 - 8 ro 0011b reserved 7 ? 4 r/w/l 0111b internal parallel port interrupt routing register to serirq slot (ipp_routing[3:0]) 0000, 1101: no interrupt; 0001: irq1 slot; 0010: smi# slot; 0011-1100: irq3-irq12 slots; 1110-1111: irq14-irq15 slots. 3 - 0 ro 1010b reserved 9.3.27 undefined register bit r/w default description 31 - 0 ro 00000000h reserved
www.ite.com.tw IT8875F v0.1 www.iteusa.com 42
www.ite.com.tw IT8875F v0.1 www.iteusa.com 43 interrupt controller (intc) 10. interrupt controller (intc) the interrupts are issued from the modules of internal parallel port, gpio and isa interrupts. users can route the internal parallel port, gpio and one isa interrupt (pin irq0) to the corresponding interrupt. after the host detects the interrupt, it reads the interrupt request register to check which module generate d the interrupt. as the controller provides the feature of gathering interrupts from all modules into one register, it will help to simplify the interrupt processing. 10.1 features g all interrupts issued from the internal modules are gathered into one register g only one external interrupt output pin inta# is used to request the interrupt service g interrupt request lines from each module are high active, and the trigger modes could be set as edge or level mode. for irq0, the software interrupt bit of irq0 is used to xor with the input to generate the real interrupt to generate the high active signal to the interrupt module g each module provides an interrupt mask bit. an interrupt mask register, which is able to perform masking for each module interrupt, is also included 10.2 block diagram irr interrupt request register mux sigr s/w interrupt trigger register latch edge-trigger interrupts + + inta# to pci bus read to get int sources write to clear latched edge interrupts r w sel ier interrupt edge/level trigger register irq[15:0], ipp_irq, mask central bus i/f intc module imr interrupt mask register figure 10 - 1 . block diagram of the interrupt controller
www.ite.com.tw IT8875F v0.1 www.iteusa.com 44 it8 875f 10.3 register descriptions table 10 - 1 . list of intc registers name address register size access size interrupt request register s (irr) intc_base + 0~2h 3 1 interrupt mask register s (imr) intc_base + 4~6h 3 1 interrupt trigger mode (edge/level) register s (ier) intc_base + 8~ah 3 1 s/w interrupt trigger register s (itr) intc_base + c~eh 3 1 10.3.1 interrupt request register 1 (irr1r) ? offset intc_base + 0h bit r/w default description 7 - 0 r/w1c 00h external irq[7:0] status (status_irq[7:0]) 0: no interrupts request. 1: interrupt in service or pending. 10.3.2 interrupt request register 2 (irr 2 r) ? offset intc_base + 1h bit r/w default description 7 ? 0 r/w1c 00h external irq[15:8] status (status_irq[15:8]) 0: no interrupts request. 1: interrupt in service or pending. 10.3.3 interrupt request register 3 (irr 3 r) ? offset intc_base + 2h bit r/w default description 7 - 4 ro 0000b reserved. 3 r/w1c 0b reserved 2 r/w1c 0b reserved 1 r/w1c 0b internal parallel port interrupt request status (status_ipp) 0: no ipp interrupt request. 1: ipp interrupt in service or pending. 0 r/w1c 0b gpio interrupt request status (status_gpio) 0: no gpio interrupt request. 1: gpio interrupt in service or pending. 10.3.4 interrupt mask register 1 (imr1r) ? offset intc_base + 4h bit r/w default description 7 - 0 r/w 00h external irq[7:0] mask (mask_irq[7:0]) 0: interrupts is unmasked. 1: interrupt is masked. 10.3.5 interrupt mask register 2 (imr2r) ? offset intc_base + 5h bit r/w default description 7 - 0 r/w 00h external irq[15:8] mask (mask_irq[15:8]) 0: interrupts is unmasked. 1: interrupt is masked.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 45 interrupt controller (intc) 10.3.6 interrupt mask register 3 (imr3r) ? offset intc_base + 6h bit r/w default description 7 - 4 ro 0000b reserved 3 r/w 0b reserved 2 r/w 0b reserved 1 r/w 0b internal parallel port interrupt mask (mask_ipp) 0: ipp interrupt is unmasked. 1: ipp interrupt is masked. 0 r/w 0b reserved 10.3.7 interrupt edge/level trigger mode register 1 (ier1r) ? offset intc_base + 8h bit r/w default description 7 - 0 r/w 00h external irq[7:0] interrupt trigger mode (edge_irq[7:0]) 0: interrupt is edge trigger . 1: interrupt is level trigger. 10.3.8 i nterrupt edge/level trigger mode register 2 (ier2r) ? offset intc_base + 9h bit r/w default description 7 - 0 r/w 00h external irq[15:8] interrupt trigger mode (edge_irq[15:8]) 0: interrupt is edge trigger . 1: interrupt is level trigger. 10.3.9 interrupt edge/level trigger mode register 3 (ier3r) ? offset intc_base + ah bit r/w default description 7 - 4 ro 0000b reserved 3 r/w 0b reserved 2 r/w 0b reserved 1 r/w 0b internal parallel port interrupt trigger mode (edge_ipp) 0: ipp interrupt is edge trigger . 1: ipp interrupt is level trigger. 0 r/w 0b reserved 10.3.10 s/w interrupt generate register 1 (sigr1r) ? offset intc_base + ch bit r/w default description 7 - 0 r/w 00h generate s/w interrupt on irq[7:0] p ath (sw_irq[7:0]) 0: no s/w i interrupt . 1: generate s/w interrupt. 10.3.11 s/w interrupt generate register 2 (sigr2r) ? offset intc_base + dh bit r/w default description 7 - 0 r/w 00h generate s/w interrupt on irq[15:8] p ath (sw_irq[15:8]) 0: no s/w i nterrupt . 1: generate s/w interrupt.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 46 it8 875f 10.3.12 s/w interrupt generate register 3 (sigr3r) ? offset intc_base + eh bit r/w default description 7 - 4 ro 0000b reserved 3 r/w 0b reserved 2 r/w 0b reserved 1 r/w 0b generate s/w i nterrupt on p ath ipp i nterrupt p ath (sw_ipp) 0: no s/w interrupt . 1: generate s s/w interrupt. 0 r/w 0b reserved
www.ite.com.tw IT8875F v0.1 www.iteusa.com 47 parallel port 11. parallel port 11.1 overview the IT8875F incorporates one multi-mode high performance parallel port, which supports the ibm at, ps/2 compatible bi-directional parallel port (spp), the enhanced parallel port (epp) and the extended capabilities port (ecp). please refer to the IT8875F configuration registers and configuration description for information on enabling/ disabling, changing the base address of the parallel port, and selecting the mode of operation. table 11 - 1 . parallel port connector in different modes host connector pin no. spp epp ecp 1 76 stb# write# nstrobe 2-9 71-68,66-63 pd0 - 7 pd0 - 7 pd0 - 7 10 62 ack# intr nack 11 61 busy wait# busy periphack(2) 12 60 pe (nu) (1) perror nackreverse(2) 13 59 slct (nu) (1) select 14 77 afd# dstb# nautofd hostack(2) 15 75 err# (nu) (1) nfault nperiphrequest(2) 16 73 init# (nu) (1) ninit nreverserequest(2) 17 74 slin# astb# nselectin notes : 1. nu: not used 2. fast mode 3. for more information, please refer to the ieee 1284 standard. 11.2 spp and epp modes table 11 - 2 . address map and bit map for spp and epp modes register address i/o d0 d1 d2 d3 d4 d5 d6 d7 mode data port base 1+0h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 spp/epp status port base 1+1h ro tmout 1 1 err# slct pe ack# busy# spp/epp control port base 1+2h r/w stb afd init slin irqe pddir 1 1 spp/epp epp address port base 1+3h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port0 base 1+4h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port1 base 1+5h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port2 base 1+6h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port3 base 1+7h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp note 1. the base address 1 depends on the logical device configuration registers of parallel port (0x60, 0x61).
www.ite.com.tw IT8875F v0.1 www.iteusa.com 48 it8 875f (1) data port (base address 1 + 00h) this is a bi-directional 8-bit data port. the direction of data flow is determined by the bit 5 of the logic state of the control port register. it forwards directions when the bit is low and reverses when the bit is high. (2) status port (base address 1 + 01h) this is a read only register. writing to this register has no effects. the contents of this register are latched during an ior cycle. bit 7 - busy#: inverse of printer busy signal, a logic ? 0 ? means that the printer is busy and cannot accept another character. a logic ? 1 ? means that it is ready to accept the next character. bit 6 - ack#: printer acknowledge, a logic ? 0 ? means that the printer has received a character and is ready to accept another. a logic ? 1 ? means that it is still processing the last character. bit 5 - pe: paper end, a logic ? 1 ? indicates the paper end. bit 4 - slct: printer selected, a logic ? 1 ? means that the printer is on line. bit 3 - err#: printer error signal, a logic ? 0 ? means an error has been detected. bits 1, 2: reserved, these bits are always ? 1 ? when read. bit 0 - tmout: this bit is valid only in epp mode and indicates that a 10-msec timeout has occurred in epp operation. a logic ? 0 ? means no timeout occurred and a logic 1 means that a timeout error has been detected. this bit is cleared by a lreset# or by writing a logic ? 1 ? to it. when the IT8875F is selected to non-epp mode (spp or ecp), this bit is always logic ? a ? when read. (3) control port (base address 1 + 02h) this port provides all output signals to control the printer. the register can be read and written. bits 6, 7: reserved, these two bits are always ? 1 ? when read. bit 5 pddir: data port direction control, this bit determines the direction of the data port. set this bit ? 0 ? to output the data port to pd bus and ? 1 ? to input from pd bus. bit 4 irqe: interrupt request enable, setting this bit ? 1 ? enables the interrupt requests from the parallel port to the host. an interrupt request is generated by a ? 0 ? to ? 1 ? transition of the ack# signal. bit 3 slin: inverse of slin# pin, setting this bit to ? 1 ? selects the printer. bit 2 init: initiate printer, setting this bit to ? 0 ? initializes the printer. bit 1 afd: inverse of the afd# pin, setting this bit to ? 1 ? causes the printer to automatically feed after each line is printed. bit 0 stb: inverse of the stb# pin. this pin controls the data strobe signal to the printer. (4) epp address port (base address 1 + 03h) the epp address port is only available in the epp mode. when the host writes to this port, the contents of d0 -d7 are buffered and output to pd0 - pd7. the leading edge of iow (internal signal, active when i/o write cycle is on this address) causes an epp address write cycle. when the host reads from this port, the contents of pd0 - pd7 are read. the leading edge of ior (internal signal, active when i/o read cycle is on this address) causes an epp address read cycle. (5) epp data ports 0-3 (base address 1 + 04-07h) the epp data ports are only available in the epp mode. when the host writes to these ports, the contents of d0 - d7 are buffered and output to pd0 - pd7. the leading edge of iow (internal signal, active when i/o write cycle is on this address) causes an epp data write cycle. when the host reads from these ports, the contents of pd0 - pd7 are read. the leading edge of ior (internal signal, active when i/o read cycle is on this address) causes an epp data read cycle.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 49 parallel port 11.3 epp mode operation when the parallel port of the IT8875F is set in the epp mode, the spp mode is also available. if no epp address/data port address is decoded (base address + 03h- 07h), the pd bus is in the spp mode, and the output signals such as stb#, afd#, init#, and slin# are set by the spp control port. the direction of the data port is controlled by the bit 5 of the control port register. there is a 10-msec time required to prevent the system from lockup. the time has elapsed from the beginning of the iochrdy (internal signal: when active, the IT8875F will issue long wait in sync field) high (epp read/write cycle) to wait# being de-asserted. if a timeout occurs, the current epp read/write cycle is aborted and a logic ? 1 ? will be read in the bit 0 of the status port register. the host must write 0 to bits 0, 1, 3 of the control port register before any epp read/write cycle (epp spec.) the pins stb#, afd# and slin# are controlled by hardware for the hardware handshaking during epp read/write cycle. (1) epp address write the host writes a byte to the epp address port (base address + 03h). the chip drives d0 - d7 onto pd0 - pd7. the chip drives iochrdy low and asserts write# (stb#) and astb# (slin#) after iow becomes active. peripheral de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts astb#, latches the address from d0 - d7 to pd bus and releases iochrdy, allowing the host to complete the i/o write cycle. peripheral asserts wait#, indicating that it acknowledges the termination of the cycle. then, the chip de-asserts write to terminate the cycle. (2) epp address read the host reads a byte from the epp address port. the chip drives pd bus to tri-state for peripheral to drive. the chip drives iochrdy low and asserts astb# after ior becomes active. peripheral drives the pd bus valid and de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts astb#, latches the address from pd bus to d0 -d7 and releases iochrdy, allowing the host to complete the i/o read cycle. peripheral drives the pd bus to tri-state and then asserts wait#, indicating that it acknowledges the termination of the cycle (3) epp data write the host writes a byte to the epp data port (base address +04h - 07h). the chip drives d0- d7 onto pd0 -pd7. the chip drives iochrdy low and asserts write# (stb#) and dstb (afd#) after iow becomes active. peripheral de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts dstb#, latches the data from d0 - d7 to the pd bus and releases iochrdy, allowing the host to complete the i/o write cycle. peripheral asserts wait#, indicating that it acknowledges the termination of the cycle. then, the chip de-asserts write to terminate the cycle. (4) epp data read the host reads a byte from the epp data port. the chip drives pd bus to tri-state for peripheral to drive. the chip drives iochrdy low and asserts dstb# after ior becomes active. peripheral drives pd bus valid and de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts dstb#, latches the data from pd bus to d0 - d7 and releases iochrdy, allowing the host to complete the i/o read cycle. peripheral tri-states the pd bus and then asserts wait#, indicating that it acknowledges the termination of the cycle.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 50 it8 875f 11.4 ecp mode operation this mode is both software and hardware compatible with that of the existing parallel ports, allowing ecp to be used as a standard lpt port when the ecp mode is not required. due to the variation of system platform, dma mode is not supported in it8875 ecp mode, only pio mode can be operated. a 16-byte fifo is implemented in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. the port supports automatic handshaking for the standard parallel port to improve compatibility and expedite the mode transfer. it also supports run-length encoded (rle) decompression in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times a byte has been repeated. the IT8875F does not support hardware compression. for a detailed description, please refer to ? extended capabilities port protocol and isa interface standard ? . table 11 - 3 . bit map of the ecp registers register d7 d6 d5 d4 d3 d2 d1 d0 data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field dsr nbusy nack perror select nfault 1 1 1 dcr 1 1 pddir irqe selectin ninit autofd strobe cfifo parallel port data fifo ecpdfifo ecp data fifo tfifo test fifo cnfga 0 0 0 1 0 0 0 0 cnfgb 0 intrvalue 0 0 0 0 0 0 ecr mode nerrintren 0 serviceintr full empty (1) ecp register definitions table 11 - 4 . ecp register definitions name address attribute ecp mode function data base 1 +000h r/w 000-001 data register ecpafifo base 1 +000h r/w 011 ecp fifo (address) dsr base 1 +001h r/w all status register dcr base 1 +002h r/w all control register cfifo base 2 +000h r/w 010 parallel port data fifo ecpdfifo base 2 +000h r/w 011 ecp fifo (data) tfifo base 2 +000h r/w 110 test fifo cnfga base 2 +000h ro 111 configuration register a cnfgb base 2 +001h r/w 111 configuration register b ecr base 2 +002h r/w all extended control register notes 1: the base address 1 depends on the logical device configuration registers of parallel port (0x60, 0x61). 2: the base address 2 depends on the logical device configuration registers of parallel port (0x62, 0x63).
www.ite.com.tw IT8875F v0.1 www.iteusa.com 51 parallel port (2) ecp mode descriptions table 11 - 5 . ecp mode descriptions mode description 000 standard parallel port mode 001 ps/2 parallel port mode 010 parallel port fifo mode 011 ecp parallel port mode 110 test mode 111 configuration mode note: please refer to the ecp regist er description on pages 53-54 for a detailed description of the mode selection. (3) ecp pin descriptions table 11 - 6 . ecp pin descriptions name type description nstrobe (hostclk) o used for handshaking with busy to write data and addresses into the peripheral device pd0~pd7 i/o address or data or rle data nack (periphclk) i used for handshaking with nautofd to transfer data from the peripheral device to the host. busy (periphack) i the peripheral uses this signal for flow control in the forward direction (hand- shaking with nstrobe). in the reverse direction, this signal is used to determine whether a command or data information is present on pd0~pd7. perror (nackreverse) i used to acknowledge ninit from the peripheral which drives this signal low, allowing the host to drive the pd bus. select i printer on-line indication nautofd (hostack) o in the reverse direction, it is used for handshaking between the nack and the host. when it is asserted, a peripheral data byte is requested. in the forward direction, this signal is used to determine whether a command or data information is present on pd0 ~ pd7. nfault (nperiphrequest) i in the forward direction (only), the peripheral is allowed (but not required) to assert this signal (low) to request a reverse transfer while in ecp mode. the signal provides a mechanism for peer-to-peer communication. it is typically used to generate an interrupt to host, which has the ultimate control over the transfer direction. ninit (nreverserequest) o the host may drive this signal low to place the pd bus in the reverse direction. in the ecp mode, the peripheral is permitted to drive the pd bus when ninit is low, and nselect is high nselectin (1284 active) o always inactive (high) in the ecp mode.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 52 it8 875f (4) data port (base 1+00h, modes 000 and 001) its contents will be cleared by a reset. in a write operation, the contents of the data fields are latched by the data register. the contents are then sent without being inverted to pd0~ pd7. in a read operation, the contents of data ports are read and sent to the host. (5) ecpafifo port (address/rle) (base 1 +00h, mode 011) any data byte written to this port are placed in the fifo and tagged as an ecp address/rle. the hardware then automatically sends this data to the peripheral. operation of this port is valid only in the forward direction (dcr(5)=0). (6) device status register (dsr) (base 1 +01h, mode all) bits 0, 1 and 2 of this register are not implemented. these bit states are remained at high in a read operation of the printer status register. dsr(7): this bit is the inverted level of the busy input. dsr(6): this bit is the state of the nack input. dsr(5): this bit is the state of the perror input. dsr(4): this bit is the state of the select input. dsr(3): this bit is the state of the nfault input. dsr(2)~dsr(0): these bits are always 1. (7) device control register (dcr) (base 1+02h, mode all) bits 6 and 7 of this register have no function. they are set high during the read operation, and cannot be written. contents in bits 0~5 are initialized to 0 when the reset pin is active. dcr(7)~dcr(6): these two bits are always high. dcr(5): except in the modes 000 and 010, setting this bit low means that the pd bus is in output operation; setting it high, in input operation. this bit will be forced to low in mode 000. dcr(4): setting this bit high enables the interrupt request from peripheral to the host due to a rising edge of the nack input. dcr(3): it is inverted and output to selectin. dcr(2): it is output to ninit without inversion. dcr(1): it is inverted and output to nautofd. dcr(0): it is inverted and output to nstrobe. (8) parallel port data fifo (cfifo) (base 2+00h, mode 010) bytes written to this fifo are sent by a hardware handshake to the peripheral according to the standard parallel port protocol. this operation is only defined for the forward direction. (9) ecp data fifo (ecpdfifo) (base 2+00h, mode 011) when the direction bit dcr(5) is 0, bytes written to this fifo are sent by hardware handshaking to the peripheral according to the ecp parallel port protocol. when dcr(5) is 1, data bytes from the peripheral to this fifo are read in an automatic hardware handshaking. the host can receive these bytes by performing read operations from this fifo.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 53 parallel port (10) test fifo (tfifo) (base 2+00h, mode 110) the host may operate read/write to this fifo in any direction. data in this fifo will be displayed on the pd bus without using hardware protocol handshaking. the tfifo will not accept new data after it is full. making a read from an empty tfifo causes the last data byte to be returned. (11) configuration register a (cnfga) (base 2+00h, mode 111) this read only register indicates to the system that interrupts are isa-pulses compatible. this is an 8-bit implementation by returning a 10h. (12) configuration register b (cnfgb) (base 2+01h, mode 111) this register is read only. cnfgb(7): logic 0 read indicates that the chip does not support hardware rle compression. cnfgb(6): reserved. cnfgb(5)~cnfg(3): a value 000 read indicates that the interrupt must be selected with jumpers. cnfgb(2)~cnfg(0): reserved (13) extended control register (ecr) (base 2+02h, mode all) ecp function control register. ecr(7)~ecr(5): these bits are used for read/write and mode selection. table 11 - 7 . extended control register (ecr) mode and description ecr mode and description 000 standard parallel port mode. the fifo is reset and the direction bit dcr(5) is always 0 (forward direction) in this mode. 001 ps/2 parallel port mode. it is similar to the spp mode, except that the dcr(5) is read/write. when dcr(5) is 1, the pd bus is tri-state. reading the data port returns the value on the pd bus instead of the value of the data register. 010 parallel port data fifo mode. this mode is similar to the 000 mode, except that the host writes the data bytes to the fifo. the fifo data is then transmitted to the peripheral using the standard parallel port protocol automatically. this mode is only valid in the forward direction (dcr(5)=0). 011 ecp parallel port mode. in the forward direction, bytes placed into the ecpdfifo and ecpafifo are placed in a single fifo and automatically transmitted to the peripheral under the ecp protocol. in the reverse direction, bytes are transmitted to the ecpdfifo from the ecp port. 100, 101 reserved, not defined 110 test mode. in this mode, the fifo may be read from or written to, but it cannot be sent to peripheral. 111 configuration mode. in this mode, the cnfga and cnfgb registers are accessible at 0x400 and 0x401.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 54 it8 875f ecr(4): nerrintren, read/write, valid in ecp(011) mode 1: disable the interrupt generated on the asserting edge of the nfault input. 0: enable the interrupt pulse on the asserting edge of the nfault. an interrupt pulse will be generated if nfault is asserted, or if this bit is written from 1 to 0 in the low-level nfault. ecr(3): reserved ecr(2): serviceintr, read/write 1: disable all service interrupts 0: enable the service interrupts. this bit will be set to ? 1 ? by hardware when one of the three service interrupts has occurred. writing ? 1 ? to this bit will not generate an interrupt. case 1: dcr(5)=0 this bit is set to 1 (a service interrupt generated) whenever there are writeintrthreshold or more bytes space free in the fifo. case 2: dcr(5)=1 this bit is set to 1 (a service interrupt generated) whenever there are readintrthreshold or more valid bytes to be read from the fifo. ecr(1): full, read-only 1: the fifo is full and cannot accept another byte. 0: the fifo has at least 1 free data byte space. ecr(0): empty, read only 1: the fifo is empty. 0: the fifo contains at least 1 data byte. (14) mode switching operation in programmed i/o control (mode 000 or 001), p1284 negotiation and all other tasks that happen before data is transferred is software-controlled. setting mode to 011 or 010 will cause the hardware to perform an automatic control-line handshaking, transferring information between the fifo and the ecp port. from the mode 000 or 001, any other mode may be immediately switched to from another mode. to change direction, the mode must first be set to 001. in the extended forward mode, the fifo must be cleared and all the signals must be de-asserted before returning to mode 000 or 001. in ecp reverse mode, all data must be read from the fifo before returning to mode 000 or 001. usually, unneeded data is accumulated during ecp reverse handshaking, when the mode is changed during a data transfer. in such conditions, nautofd will be de-asserted regardless of the transfer state. to avoid bugs during handshaking signals, these guidelines must be followed. (15) software operation (ecp) before the ecp operation can begin, it is first necessary for the host to switch the mode to 000 in order to negotiate with the parallel port. during this process, the host determines whether peripheral supports the ecp protocol. after this negotiation is completed, the mode is set to 011 (ecp). to enable the drivers, direction must be set to 0. both strobe and autofd are set to 0, causing nstrobe and nautofd signals to be de-asserted. all fifo data transfers are pword wide and pword aligned. permitted only in the forward direction, address/rle transfers are byte-wide. the ecp address/rle bytes may be automatically sent by writing to the ecpafifo. similarly, data pwords may be automatically sent via the ecpdfifo.
www.ite.com.tw IT8875F v0.1 www.iteusa.com 55 parallel port to change directions, the host switches mode to 001. it then negotiates either the forward or reverse channel, sets direction to 1 or 0, and finally switches mode to 001. if the direction is set to 1, the hardware performs handshaking for each ecp data byte read, then tries to fill the fifo. at this time, pwords may be read from the ecpdfifo while it retains data. it is also possible to perform the ecp transfers by handshaking with individual bytes under programmed control in mode = 001, or 000, even though this is a comparatively time-consuming approach. (16) interrupts it is necessary to generate an interrupt when any of the following states are reached. serviceintr = 0, direction = 0, and the number of pwords in the fifo is greater than or equal to writeintrthreshold. serviceintr = 0, direction = 1, and the number of full pwords in the fifo is greater than or equal to readintrthreshold. nerrintren = 0 and nfault goes from high to low or when nerrintren is set from 1 to 0 and nfault is asserted. ackinten = 1. in current implementations of using existing parallel ports, the interrupt generated may be either edge or level type. (17) interrupt driven programmed i/o it is also possible to use an interrupt-driven programmed i/o to execute either ecp or parallel port fifos. an interrupt will occur in the forward direction when serviceintr is 0 and the number of free pwords in the fifo is equal to or greater than writeintrthreshold. if either of these conditions is not met, it may be filled with writeintrthreshold pwords. an interrupt will occur in the reverse direction when serviceintr is 0 and the number of available pwords in the fifo is equal to readintrthreshold. if it is full, the fifo can be completely emptied in a single burst. if it is not full, only a number of pwords equal to readintrthreshold may be read from the fifo in a single burst. in the test mode, software can determine the values of writeintrthreshold, readintrthreshold, and fifo depth while accessing the fifo.
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 57 dc characteristics 12. dc characteristics absolute maximum ratings power supply ( v cc ) ....................... -0.3v to 3.6/6.0v input voltage .......................... -0.3v to vcc + 0.3v output voltage ....................... -0.3v to vcc + 0.3v storage temperature ....................... -40 c to 125 c *comments stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (operation condition vcc = 4.75v~5.25v, vcc3=3.0v~3.6v, tj=0 c~70 c) symbol parameter condition min. typ. max. unit v il input low voltage for 5v cell ttl - - 0.8 v v il input low voltage for 3.3v cell cmos - - 0.3*vcc v v ih input high voltage for 5v cell ttl 2.2 - - v v ih input high voltage for 3.3v cell cmos 0.7*vcc - - v vt- schmitt trigger negative going threshold voltage ttl - 1.10 - v vt+ schmitt trigger positive going threshold voltage ttl - 1.90 - v v ol output low voltage - - 0.4 v v oh output high voltage for 5v cell (for all parallel port outputs) ttl 2.4 - - v v oh output high voltage for 5v cell 3.5 - - v v oh output high voltage for 3.3v cell 2.3 - - v rl input pull-up resistance v il =0v or v ih =vcc - 50 - k w i il input leakage current no pull-up -1 - 1 m a i oz tri-state leakage current -1 - 1 ma c in input capacity - 5 - pf cout output capacity - 10 - pf cbid bi-directional buffer capacity - 10 - pf
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 59 package information 13. package information pqfp 128l outline dimensions unit: inches/mm 39 64 d e a a 2 a 1 102 65 103 128 38 detail "a" 1 see detail "f" seating plane e 1 b d 1 e detail "a" d y 0.10 b base metal c with plating l 1 detail "f" l gage plane y c dimension in inch dimension in mm symbol min. nom. max. min. nom. max. a - - 0.134 - - 3.40 a 1 0.010 - - 0.25 - - a 2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.677 0.685 17.00 17.20 17.40 e 1 0.547 0.551 0.555 13.90 14.00 14.10 0.020 bsc 0.5 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l 1 0.063 bsc 1.60 bsc y - - 0.004 - - 0.10 q 0 x - 7 x 0 x - 7 x notes: 1. dimensions d 1 and e 1 do not include mold protrusion, but mold mismatch is included. 2. dimension b does not include dambar protrusion. 3. controlling dimension: millimeter. e
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www.ite.com.tw IT8875F v0.1 www.iteusa.com 61 ordering information 14. ordering information part no. package IT8875F 128 pqfp

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